1. Field of the Invention
The present invention relates to a semiconductor Hall element, and more particularly, to a highly-sensitive Hall sensor capable of eliminating an offset voltage.
2. Description of the Related Art
At first, the principle for detecting magnetism of a Hall element is described. When a magnetic field is applied perpendicularly to a current flowing through a substance, an electric field, which causes a Hall voltage, is generated in a direction perpendicular to both the current and the magnetic field.
Consider a Hall element illustrated in FIG. 2. When the width of a Hall sensing portion 1 which generates the Hall voltage according to the magnetic field is represented by W, the length thereof is represented by L, electron mobility thereof is represented by p, an applied voltage of a power source 2 for supplying a current is represented by Vdd, and an applied magnetic field is represented by B, the Hall voltage VH appearing on a voltmeter 3 is expressed by:VH=μB(W/L)Vdd, and magnetic sensitivity Kh of the Hall element is expressed by:Kh=μ(W/L)Vdd. The expressions above show that one of the methods for increasing the sensitivity of the Hall element is to increase the ratio W/L.
On the other hand, in an actual Hall element, an output voltage is generated even when no magnetic field is applied. The output voltage under a zero magnetic field is called offset voltage. It is considered that an imbalanced potential distribution inside the element generates the offset voltage due to mechanical stress applied to the element from the outside or due to misalignment occurring in a manufacturing process.
The following methods are generally employed to compensate the offset voltage to a level allowable for practical use through cancellation or the like.
The first method uses an offset cancellation circuit utilizing spinning current as illustrated in FIG. 3.
A Hall sensing portion 10 has a symmetrical shape and includes four terminals T1, T2, T3, and T4, in which a control current is supplied between one pair of input terminals and an output voltage is obtained between the other pair of output terminals. When one pair of the terminals T1 and T2 of the Hall sensing portion serves as control current input terminals, the other pair of the terminals T3 and T4 serves as Hall voltage output terminals. In this case, when a voltage Vin is applied to the input terminals, an output voltage Vh+Vos is generated between the output terminals, where Vh represents a Hall voltage proportional to a magnetic field of the Hall element and Vos represents an offset voltage. Next, with the terminals T3 and T4 serving as the control current input terminals and the terminals T1 and T2 serving as the Hall voltage output terminals, the input voltage Vin is applied between the terminals T3 and T4 to generate a voltage −Vh+Vos between the output terminals. Subtraction between the two output voltages, each obtained by applying a current flowing in one of the two directions described above, cancels the offset voltage Vos to obtain an output voltage 2Vh proportional to the magnetic field (see, for example, Japanese Patent Application Laid-open No. JP 06-186103 A).
The second method uses two Hall elements having the same shape and connected in series. Each Hall sensing portion of each Hall elements is disposed in proximity in a direction in which the two Hall elements are orthogonal to each other, to thereby eliminate the unbalance of voltages caused by stress (see, for example, Japanese Patent Application Laid-open No. JP 62-208683 A).
However, in the first method, (JP 06-186103 A), if the currents, which are applied to the Hall sensing portion in two directions, or the output Hall voltages depend on the shape of the Hall element, the offset voltage cannot be eliminated utilizing spinning current. The Hall element is hence required to have a symmetrical shape and the four terminals are also required to have the same shape. In the conventional method, the same terminal serves as both the Hall voltage output terminal and the control current input terminal. Accordingly, in order to eliminate the offset voltage, the terminals having the two functions are all required to have the same shape. Since each of the terminals alternately serves as the Hall voltage output terminal and the control current input terminal, it is impossible to assign a shape and an arrangement suitable for the respective functions. As described above, the sensitivity and the offset voltage of the Hall element changes depending also on the shape and the arrangement of the four terminals, and hence there is a problem of how to select the shape and the arrangement of the terminals.
Further, in the second method (JP 62-208683 A), the ratio W/L can be determined arbitrarily, permitting the increase in the sensitivity. However, since a plurality of the Hall elements are used, there is a problem that the chip size increases, leading to an increase in cost.
In addition, the offset voltage elimination by the utilizing spinning current is insufficient to eliminate the offset voltage in some cases. The reason is described as follows.
The Hall element is represented by an equivalent circuit illustrated in FIG. 4. The Hall element is represented by a bridge circuit in which the four terminals are connected to one another via four resistors R1, R2, R3, and R4. When the Hall element has a symmetrical shape, the four resistors R1, R2, R3, and R4 have the same resistance. In an actual case, however, the resistance varies depending on stress, processing accuracy in the manufacturing process, and the like. In the manner as described above, one output voltage is subtracted from the other, each of which is obtained by supplying a current flowing in one of the two directions, to thereby cancel the offset voltage.
Consider the case where the applied magnetic field is zero. When the voltage Vin is applied between the pair of the terminals T1 and T2 of the Hall element, a Hall voltage expressed below comes out between the other pair of the terminals T3 and T4.Vouta=(R2*R4−R1*R3)/(R1+R4)/(R2+R3)*VinOn the other hand, when the voltage Vin is applied between the terminals T3 and T4, a Hall voltage expressed below comes out between the terminals T1 and T2.Voutb=(R1*R3−R2*R4)/(R3+R4)/(R1+R2)*VinThe difference between the output voltages in two directions, that is, the offset voltage is expressed below.Vos=Vouta−Voutb=(R1−R3)*(R2−R4)*(R2*R4−R1*R3)/(R1+R4)/(R2+R3)/(R3+R4)/(R1+R2)*VinIn this case, the offset voltage can be eliminated under the condition in which the denominator of the right side “(R1−R3)*(R2−R4)*(R2*R4−R1*R3)” is 0. Accordingly, the offset voltage can be cancelled even when the resistances of the resistors R1, R2, R3, and R4 in the equivalent circuit are different from one another. However, if the resistances of the resistors R1, R2, R3, and R4 vary between one current application direction and the other, that is, if the resistances of the four resistors R1, R2, R3, and R4 vary between a case when the voltage Vin is applied between one pair of the terminals T1 and T2 of the Hall element and another case when the voltage Vin is applied between the other pair of the terminals T3 and T4, the offset voltage Vos does not satisfy the above-mentioned expression and cannot be cancelled.
FIG. 5 is a cross-sectional view of a general Hall element. A peripheral portion of an N-type doped region 102 to become the Hall sensing portion is surrounded by a P-type impurity region for isolation. When a voltage is applied between Hall current application terminals, a depletion layer expands at a boundary between the Hall sensing portion and its peripheral portion. No Hall current flows in the depletion layer, and hence in a region of the expanding depletion layer, the Hall current is suppressed to increase the resistance. Further, the width of the depletion layer depends on the applied voltage. Accordingly the resistances of the resistors R1, R2, R3, and R4 of the equivalent circuit illustrated in FIG. 4 change depending on the voltage application direction, and hence the offset cancellation circuit cannot cancel the magnetic offset.